As operating frequencies of integrated circuits continue to rise, the effects of inductance on circuit performance are becoming increasingly important. For example, for integrated circuits operating near or above the gigahertz frequency range, the mutual inductance with neighboring signal wires may create signal-integrity problems (such as noise and cross talk). Consequently, the effective modeling and analysis of mutual inductance has become an issue of great interest for high-speed circuit designers and for electronic design automation (EDA) software vendors that develop the tools used to create, simulate, verify, and optimize the designs of integrated circuits (e.g., RF circuits comprising intentional inductors) and to provide bounds for effects due to inductance.
Intentional inductors are often used as components in RF (radio frequency) analog designs, particularly in telecommunication applications. Design and manufacturing considerations usually favor spacing the different inductors closely together in order to minimize the occupied area. To be able to place the inductors safely, however, a designer desirably has a quantitative measure of the electromagnetic noise that one inductor induces on another. The noise figures can be evaluated, for example, in terms of the electrical parameter resistance, inductance, and capacitance matrices (PLC) for the system.